Reverse Biasing in a P-channel JFET 
1. What happens to the depletion region in a P-channel JFET when the gate-source voltage (V_GS) is made more positive?
2. In a P-channel JFET, what is the effect of increasing the gate-source voltage (V_GS) beyond the pinch-off voltage (V_P)?
3. How does the drain-source voltage (V_DS) affect the drain current (I_D) in the reverse bias condition of a P-channel JFET?
4. In a P-channel JFET, what happens when the gate-source voltage (V_GS) is equal to the pinch-off voltage (V_P)?
5. What is the characteristic of the drain current (I_D) in the saturation region of a P-channel JFET under reverse bias?
6. In a P-channel JFET, what happens to the channel conductivity when the gate-source voltage (V_GS) is made more positive?
7. What is the typical reverse leakage current in the gate-source junction of a P-channel JFET?
8. In a P-channel JFET, what condition indicates that the device is in the ohmic region during reverse bias?
9. What is the effect of reverse biasing the gate-source junction on the overall impedance of a P-channel JFET?
10. In the context of reverse biasing in a P-channel JFET, what does a higher magnitude of gate-source voltage (V_GS) typically indicate?